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17,000 tokens per second with a model etched into silicon: AMD buys Taalas

8 min read
Taalas HC1 accelerator card, with the main chip visible on the blue PCB

AMD announced on August 6 that it had acquired Taalas, a Toronto startup that makes chips where the AI model is not loaded: it comes etched into the silicon. Its demonstrator, the HC1, generates 16,960 tokens per second per user. An NVIDIA H200, on the same model, generates 230.

The number is real. What almost nobody clarified is what it is measured against and at what cost: that chip runs exactly one model, Llama 3.1 8B, and running another one requires manufacturing a new chip.

What Taalas is

Taalas was founded in August 2023 in Toronto and came out of stealth in February 2026. It is led by Ljubisa Bajic, co-founder and former CEO of Tenstorrent, who previously designed architectures at AMD and NVIDIA.

The numbers explain why AMD paid attention: it raised more than $200 million from Pierre Lamond, Quiet Capital, and Fidelity — the last $169 million in February — but according to Futurum Group it spent about $30 million and reached functional silicon with 24 people. Its entire software stack is maintained by a single engineer.

AMD did not disclose how much it paid. The deal remains subject to regulatory approvals, and Bajic will report to Vamsi Boppana, who leads AMD’s AI group.

Ljubisa Bajic, co-founder and CEO of Taalas, wearing a Tenstorrent jacket, the company he founded earlier
Image: Tenstorrent.

How a model is etched into silicon

A conventional accelerator stores weights in HBM memory and brings them onto the chip for each operation. That round trip is the bottleneck in inference, and also the reason memory shortages pushed prices upward across half the market.

Taalas eliminates it by removing HBM from the design. The weights go into a mask ROM manufactured inside the chip itself: each cell stores a 4-bit parameter and performs the multiplication with a single transistor. On-board SRAM is left for the KV cache and fine-tuning adapters, the only things that change between queries.

The HC1 is manufactured on TSMC’s N6 node, uses an 815 mm² die, and consumes about 250 W, according to the breakdown from EE Times. Ten cards fit into a standard air-cooled server, at 2.5 kW.

That is not the most interesting part; the cost is. A chip per model would be unworkable if the whole design had to be redone, and Taalas customizes only 2 of the more than 100 mask layers: from model to finished chip takes two months. The company sums it up in the phrase that leads its site: the model is the computer.

Taalas diagram showing a GPT model converted into dedicated hardware
Image: Taalas.

What the 17,000 tokens per second figure measures

The HC1’s 16,960 tokens per second are per user, running Llama 3.1 8B, and come from Taalas’s own measurements: no third party has validated them yet. The figure measures how quickly the chip generates text for a single person, not the aggregate throughput of a full server.

Bar chart comparing HC1 tokens per second per user against accelerators from NVIDIA, Groq, SambaNova, and Cerebras
Image: Taalas.
AcceleratorTokens/s per userHC1 advantage
NVIDIA H20023073×
NVIDIA B20035348×
Groq59429×
SambaNova93218×
Cerebras1,9818.5×
Taalas HC116,960—

That last column clears up a confusion that affected much of the coverage. It was reported that the HC1 is 48 times faster than NVIDIA GPUs and also that it delivers 73 times the performance of an H200. Both are correct: the 73× is measured against the H200, and the 48× against the B200, which is the current generation.

The other side of the equation is where the approach defends itself even better than on speed: 0.75 cents per million tokens on Llama 3.1 8B, and 7.6 cents on a simulated 671-billion-parameter DeepSeek-R1.

The cost of freezing a model

Llama 3.1 8B came out in July 2024. The chip that runs it at 16,960 tokens per second runs nothing else, and changing it requires redoing the two mask layers and manufacturing it again. Taalas says that re-spin costs about 100 times less than training a frontier model: that is true, and also a convenient comparison with one of the most expensive things the industry does.

The capacity ceiling is the other limit. One chip can handle about 8 billion parameters, or up to 20 billion by separating the SRAM. The HC2, expected in 2026, targets those 20 billion. A full DeepSeek-R1 would require about 30 different designs.

The comparison with Etched helps frame the landscape: both say they etch AI into silicon, and they do opposite things. Etched’s Sohu etches the transformer architecture, not the weights, which remain mutable in 144 GB of HBM3E per chip: an eight-unit server can fit a 400-billion- to 600-billion-parameter model and change it whenever needed. Taalas chose the opposite extreme.

It is a chip that cannot be updated. There is no firmware that can fix a model that has grown old.

Render of Etched’s Sohu accelerator, with the central die surrounded by HBM3E memory modules
Image: Etched.

AMD buys pieces, it does not fight head-on

Taalas fits a pattern. AMD has been buying pieces of the AI problem instead of building a training competitor against NVIDIA: Nod.ai for compilers, Silo AI for models, ZT Systems for rack assembly, Brium and the Untether AI team for inference optimization, plus Lamini and MK1. None was a better GPU; all were a missing piece of the platform.

The contrast with NVIDIA puts it in perspective. In December 2025, NVIDIA licensed Groq’s technology for about $20 billion and kept control from the outside. AMD bought the whole company, including the design flow and a team that already knows its architectures from the inside: Bajic worked there before founding Tenstorrent.

The intended use is disaggregated decoding: the prompt is processed on the flexible Instinct GPUs, and token generation moves to Taalas silicon, which is faster but single-purpose. The Helios racks are where that would coexist. AMD already has 6 gigawatts of GPUs committed with OpenAI and up to 2 with Anthropic: for a customer serving the same model at volume, a single-model chip makes the math work.

Lisa Su on AMD’s stage next to an open Instinct server node, with a Helios rack on the background screen
Image: AMD.

Conclusion

Taalas solved a real problem through the most uncomfortable path: if the model does not move, the hardware does not need to be flexible. The 16,960 tokens per second are not marketing; they are the consequence of removing external memory from the equation.

For anyone running inference at scale on a stable model — a production assistant, an API serving millions of queries from the same model — the proposition works: very low cost per token and latency no GPU can match. For any other case, a chip that becomes obsolete with the next model is a risk that is hard to justify.

AMD did not buy the HC1: it bought the flow that turns a model into masks in two months. What remains to be seen is whether that ends up in a product it sells, or in a tool for manufacturing custom silicon for the three or four customers buying gigawatts from it.

Frequently asked questions

What is a model-specific chip?

It is an integrated circuit designed to run a single AI model, with its weights etched into the silicon during manufacturing. Unlike a GPU, which loads any model from memory, it cannot run anything else: the model is part of the hardware.

Does the Taalas chip replace GPUs?

No. AMD proposes using it alongside its Instinct GPUs: the prompt is processed on the GPU, and token generation moves to the Taalas chip. Training remains exclusively GPU territory.

What happens when a new model comes out?

A new chip has to be manufactured. Taalas redoes two of the more than 100 mask layers, taking about two months from model to finished chip. The previous one keeps running the model it was born with.

When will this technology arrive in AMD products?

AMD did not give dates. The acquisition remains subject to regulatory approvals, and the company said it will integrate the technology into its accelerator roadmap and system-level solutions with Instinct GPUs.

Taalas HC1

Taalas technical demonstrator that etches the weights of Llama 3.1 8B into the silicon itself using a mask ROM. Because it does not depend on external HBM memory, it reaches 16,960 tokens per second per user, but it cannot run any other model.

ManufacturingTSMC N6 (6 nm)
Die size815 mm²
Power consumption~250 W per card
Weight storageIntegrated mask ROM, 4 bits per cell
On-board memoryProgrammable SRAM for KV cache and adapters
HBM memoryNot used
Supported modelLlama 3.1 8B (only)
Parameters per chip~8 billion (up to 20 billion by separating the SRAM)
Performance16,960 tokens per second per user
Cost per million tokens0.75 cents (Taalas estimate)
Custom mask layers2 out of more than 100
Manufacturing time per model~2 months

Pros

  • Generates 16,960 tokens per second per user, 48 times what an NVIDIA B200 delivers on the same model.
  • Removes HBM memory from the design and with it the inference bottleneck.
  • Estimated cost drops to 0.75 cents per million tokens.
  • Customizing only 2 of more than 100 mask layers makes a chip per model viable.
  • Fits in standard air-cooled servers, at 250 W per card.

Cons

  • Runs a single model: changing it requires manufacturing a new chip.
  • Llama 3.1 8B, the model it runs, is from July 2024.
  • The per-chip ceiling is around 8 billion parameters.
  • The performance figures come from Taalas itself and have no independent validation.
  • A large model like DeepSeek-R1 would require about 30 different designs.
Editorial Disclosure

Report based on official announcements and verified public sources at the time of publishing.

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